1. Field of the Invention
The present invention relates to a semiconductor storing device for reading out or writing data corresponding to a bit width of a memory cell array from/in a plurality of memory cells of the memory cell array.
2. Description of Related Art
FIG. 9 is a block diagram showing the configuration of a conventional semiconductor storing device. In FIG. 9, 101 indicates a conventional semiconductor storing device. 102 indicates a memory cell array in which a plurality of memory cells 103 are disposed in a matrix of 8 rows and 64 columns. 104 indicates each of a plurality of word lines. Each word line 104 is connected with the memory cells 103 placed in the same row. The number of word lines 104 disposed in the conventional semiconductor storing device 101 is equal to eight, and each word line 104 is connected with the sixty-four memory cells 103. 105 indicates each of a plurality of bit lines. Each bit line 105 is connected with the memory cells 103 placed in the same column. The number of bit lines 105 disposed in the conventional semiconductor storing device 101 is equal to sixty-four, and each bit line 105 is connected with the eight memory cells 103. 106 indicates a bit selector array.
107 indicates each of a plurality of bit selectors. The bit selector arrays 107 are disposed in the bit selector array 106, the number of bit selector arrays 107 is equal to thirty-two, and each bit selector 107 corresponds to the memory cells 103 of two columns adjacent to each other. Therefore, each bit selector 107 is connected with two bit lines 105, and one of the two bit lines 105 is selected in the bit selector 107 according to a signal transmitted through a bit select line 108. Data-N denoting one-bit data (xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d) represents each of data-0, data-1, data-2, . . . , and data-31, and the one-bit data-N is input to or output from each bit selector 107. In other words, the memory cell array 102 has a bit width of 32 bits, and 32-bit data is read out or written from/in the thirty-two memory cells 103 of the memory cell array 102 every read or write operation.
108 indicates each of two bit select lines. Each bit select line 108 is connected with the thirty-two bit selectors 107. In FIG. 9, only one bit select line 108 is shown for convenience. The bit select lines 108 relate to two bit lines 105 in one-to-one correspondence in the bit selectors 107.
109 indicates a row address decoder connected with one end of each word line 104. A row address signal included in an address signal is input from the outside to the row address decoder 109, and one word line 104 is selected in the row address decoder 109 according to the row address signal. 110 indicates a column address decoder connected with one end of each bit select line 108. A column address signal included in the address signal is input from the outside to the column address decoder 110, and one bit select line 108 is selected in the column address decoder 110 according to the column address signal.
FIG. 10 is a view showing a first addressing arrangement in which addresses are assigned to the memory cells 103 of the memory cell array 102, and FIG. 11 is a view showing a second addressing arrangement in which addresses are assigned to the memory cells 103 of the memory cell array 102. In FIG. 10 and FIG. 11, the sixteen addresses ranging from xe2x80x9c00xe2x80x9d to xe2x80x9c3Fxe2x80x9d are assigned to the memory cells 103 in the memory cell array 102, and each address is composed of eight bits corresponding to eight memory cells 103. As an example, xe2x80x9c1A.2xe2x80x9d denotes the second bit of the address xe2x80x9c1Axe2x80x9d. In the examples of the address assignment shown in FIG. 10 and FIG. 11, each bit selector 106 is connected with two bit lines 105. However, the number of bit lines connected with each bit selector 106 is arbitrary.
In the first addressing arrangement shown in FIG. 10, a group of addresses assigned to one group of memory cells 103 of the bit lines 105 corresponding to each bit select line 108 in each row are increased with the change of the group of memory cells 103 in a row direction (or a right direction in FIG. 10). For example, one group of addresses xe2x80x9c00xe2x80x9d, xe2x80x9c01xe2x80x9d, xe2x80x9c02xe2x80x9d and xe2x80x9c03xe2x80x9d assigned to the group of memory cells 103 of the bit lines 105 (placed on the left side in each of the bit selectors 106) corresponding to one bit select line 108 in the first row (or the top row in FIG. 10) are increased to another group of addresses xe2x80x9c20xe2x80x9d, xe2x80x9c21xe2x80x9d, xe2x80x9c22xe2x80x9d and xe2x80x9c23xe2x80x9d assigned to the group of memory cells 103 of the bit lines 105 (placed on the right side in the bit selectors 106) corresponding to the other bit select line 108 in the first row. Also, the address is consecutively increased in the row direction in each group of memory cells 103 for each row. For example, the addresses xe2x80x9c00xe2x80x9d, xe2x80x9c01xe2x80x9d, xe2x80x9c02xe2x80x9d and xe2x80x9c03xe2x80x9d of the group arranged in that order in the first row are increased in the row direction. Also, the addresses of consecutive numbers are assigned to the memory cells 103 connected with the bit lines 105 corresponding to each bit select line 108. For example, the addresses xe2x80x9c00xe2x80x9d to xe2x80x9c1Fxe2x80x9d of consecutive numbers are assigned to the memory cells 103 connected with the bit lines 105 (placed on the left side in each of the bit selectors 106) corresponding to one bit select line 108.
In the second addressing arrangement shown in FIG. 11, a group of addresses assigned to one group of memory cells 103 of the bit lines 105 corresponding to each bit select line 108 in each row are increased with the change of the group of memory cells 103 in the row direction. For example, one group of addresses xe2x80x9c00xe2x80x9d, xe2x80x9c01xe2x80x9d, xe2x80x9c02xe2x80x9d and xe2x80x9c03xe2x80x9d assigned to the group of memory cells 113 of the bit lines 105 (placed on the left side in each of the bit selectors 106) corresponding to one bit select line 108 in the first row are increased to another group of addresses xe2x80x9c04xe2x80x9d, xe2x80x9c05xe2x80x9d, xe2x80x9c06xe2x80x9d and xe2x80x9c07xe2x80x9d assigned to the group of memory cells 103 of the bit lines 105 (placed on the right side in the bit selectors 106) corresponding to the other bit select line 108 in the first row. Also, the address is consecutively increased in the row direction in each group of memory cells 103 for each row. For example, the addresses xe2x80x9c00xe2x80x9d, xe2x80x9c01xe2x80x9d, xe2x80x9c02xe2x80x9d and xe2x80x9c03xe2x80x9d of the group arranged in that order in the first row are increased in the row direction. Also, the addresses of consecutive numbers are assigned to the memory cells 103 of each row. For example, the addresses xe2x80x9c00xe2x80x9d to xe2x80x9c07xe2x80x9d of consecutive numbers are assigned to the memory cells 103 of the first row.
In case of the first addressing arrangement shown in FIG. 10, three lower bits (A2, A1, A0) of the address signal (A3, A2, A1, A0) sent from the outside are input to the row address decoder 109 as a row address signal, and the top bit (A3) of the address signal is input to the column address decoder 110 as a column address signal. In contrast, in case of the second addressing arrangement shown in FIG. 11, three upper bits (A3, A2, A1) of the address signal (A3, A2, A1, A0) sent from the outside are input to the row address decoder 109 as a row address signal, and the bottom bit (A0) of the address signal is input to the column address decoder 110 as a column address signal.
Next, an operation of the conventional semiconductor storing device 101, in which the addresses xe2x80x9c00xe2x80x9d to xe2x80x9c3Fxe2x80x9d are assigned to the memory cells 103 according to the first addressing arrangement shown in FIG. 10, will be described below.
In cases where thirty-two pieces of one-bit data corresponding to the 32-bit width of the memory cell array 102 are read out from or written in thirty-two memory cells 103 placed at addresses ranging from the first address xe2x80x9c00xe2x80x9d to the fourth address xe2x80x9c03xe2x80x9d as 32-bit data, the first word line 104 placed at the top position is selected in the row address decoder 109, and the first bit select line 108 placed at the top position is selected in the column address decoder 110 to select the first bit line 105 placed at the most-left side in each bit selector 107. Therefore, data-0 of the address xe2x80x9c00.0xe2x80x9d, data-1 of the address xe2x80x9c00.1xe2x80x9d, data-2 of the address xe2x80x9c00.2xe2x80x9d, . . . , data-7 of the address xe2x80x9c00.7xe2x80x9d, data-8 of the address xe2x80x9c01.0xe2x80x9d, . . . , data-16 of the address xe2x80x9c02.0xe2x80x9d, . . . , data-24 of the address xe2x80x9c03.0xe2x80x9d, . . . and data-31 of the address xe2x80x9c03.7xe2x80x9d are read out from or written in the thirty-two memory cells 103 placed at the addresses xe2x80x9c00xe2x80x9d to xe2x80x9c03xe2x80x9d as 32-bit data.
Accordingly, 32-bit data can be read out from or written in the memory cell array 102 every access operation in case of the first addressing arrangement.
Also, in cases where thirty-two pieces of one-bit data corresponding to the 32-bit width of the memory cell array 102 are read out from or written in thirty-two memory cells 103 placed from the second address xe2x80x9c01xe2x80x9d to the fifth address xe2x80x9c04xe2x80x9d as 32-bit data, because the top memory cell 103 placed at the top of the memory cells 103 of the second address xe2x80x9c01xe2x80x9d is placed in the middle of the memory cells 103 of one row, two access operations are performed. In detail, in the first access operation, the first word line 104 from the top is selected in the row address decoder 109, and the first bit select line 108 from the top is selected in the column address decoder 110 to select the first bit line 105 placed on the most-left side in each bit selector 107. Therefore, twenty-four pieces of one-bit data denoting data-8 to data-31 are read out from or written in the twenty-four memory cells 103 of the addresses xe2x80x9c01xe2x80x9d to xe2x80x9c03xe2x80x9d. In this case, though eight pieces of one-bit data are undesirably read out from or written in the eight memory cells 103 of the address xe2x80x9c00xe2x80x9d as data-0 to data-7, these eight pieces of one-bit data are disregarded. Thereafter, in the second access operation, the second word line 104 from the top is selected in the row address decoder 109, and the first bit select line 108 from the top is again selected in the column address decoder 110 to select the first bit line 105 placed on the most-left side in each bit selector 107. Therefore, eight pieces of one-bit data denoting data-0 to data-7 are read out from or written in the eight memory cells 103 of the address xe2x80x9c04xe2x80x9d. In this case, though twenty-four pieces of one-bit data are undesirably read out from or written in the twenty-four memory cells 103 of the addresses xe2x80x9c05xe2x80x9d to xe2x80x9c07xe2x80x9d as data-8 to data-31, these twenty-four one-bit data are disregarded. Therefore, 32-bit data is obtained by combining the twenty-four pieces of one-bit data of the first access operation and the eight pieces of one-bit data of the second access operation. In this case, to disregard the eight pieces of one-bit data in the first access operation and to disregard the twenty-four pieces of one-bit data in the second access operation, it is impossible to simultaneously perform the first access operation and the second access operation.
Accordingly, 32-bit data can be read out from or written in the memory cell array 102 every two access operations in case of the first addressing arrangement.
Next, an operation of the conventional semiconductor storing device 101, in which the addresses xe2x80x9c00xe2x80x9d to xe2x80x9c3Fxe2x80x9d are assigned to the memory cells 103 according to the second addressing arrangement shown in FIG. 11, will be described below.
In cases where thirty-two pieces of one-bit data corresponding to the 32-bit width of the memory cell array 102 are read out from or written in thirty-two memory cells 103 of the addresses xe2x80x9c00xe2x80x9d to xe2x80x9c03xe2x80x9d as 32-bit data, the first word line 104 placed at the top position is selected in the row address decoder 109, and the first bit select line 108 placed at the top position is selected in the column address decoder 110 to select the first bit line 105 placed on the most-left side in each bit selector 107. Therefore, thirty-two pieces of one-bit data denoting data-0 to data-31 are read out from or written in the thirty-two memory cells 103 of the addresses xe2x80x9c00xe2x80x9d to xe2x80x9c03xe2x80x9d.
Accordingly, 32-bit data can be read out from or written in the memory cell array 102 every access operation in the second addressing arrangement.
Also, in cases where thirty-two pieces of one-bit data corresponding to the 32-bit width of the memory cell array 102 are read out from or written in thirty-two memory cells 103 of the addresses xe2x80x9c01xe2x80x9d to xe2x80x9c04xe2x80x9d as 32-bit data, because the top memory cell 103 placed at the top among the memory cells 103 of the second address xe2x80x9c01xe2x80x9d is placed in the middle of the memory cells 103 of one row, two access operations are performed. In detail, in the first access operation, the first word line 104 placed at the top position is selected in the row address decoder 109, and the first bit select line 108 placed at the top position is selected in the column address decoder 110 to select the first bit line 105 placed on the most-left side in each bit selector 107. Therefore, twenty-four pieces of one-bit data denoting data-8 to data-31 are read out from or written in the twenty-four memory cells 103 of the addresses xe2x80x9c01xe2x80x9d to xe2x80x9c03xe2x80x9d.
In this case, though eight pieces of one-bit data are undesirably read out from or written in the eight memory cells 103 of the address xe2x80x9c00xe2x80x9d as data-0 to data-7, these eight pieces of one-bit data are disregarded. Thereafter, in the second access operation, the first word line 104 placed at the top position is again selected in the row address decoder 109, and the second bit select line 108 from the top is selected in the column address decoder 110 to select the second bit line 105 from the left in each bit selector 107. Therefore, eight pieces of one-bit data denoting data-0 to data-7 are read out from or written in the eight memory cells 103 of the address xe2x80x9c04xe2x80x9d. In this case, though twenty-four pieces of one-bit data are undesirably read out from or written in the twenty-four memory cells 103 of the addresses xe2x80x9c05xe2x80x9d to xe2x80x9c07xe2x80x9d as data-8 to data-31, these twenty-four pieces of one-bit data are disregarded. Therefore, 32-bit data is obtained by combining the twenty-four pieces of one-bit data of the first access operation and the eight pieces of one-bit data of the second access operation. In this case, too disregard the eight pieces of one-bit data in the first access operation and to disregard the twenty-four pieces of one-bit data in the second access operation, it is impossible to simultaneously perform the first access operation and the second access operation.
Accordingly, 32-bit data can be read out from or written in the memory cell array 102 every two access operations in the second addressing arrangement.
Because the conventional semiconductor storing device 101 has the above-described configuration, in cases where the memory cell 103 placed at the top among the memory cells 103 of pieces of one-bit data (for example, thirty-two pieces of one-bit data) planned to be read out or written in correspondence to the bit width (for example, 32 bits) of the memory cell array 102 is placed in the middle of the memory cells 103 of one row or is not placed at the top of one row, two access operations are required to obtain the pieces of one-bit data corresponding to the bit width of the memory cell array 102. Therefore, a problem has arisen that the read or write operation is troublesome in cases where the pieces of one-bit data corresponding to the bit width of the memory cell array 102 are read out from or written in the memory cell array 102.
An object of the present invention is to provide, with due consideration to the drawbacks of the conventional semiconductor storing device 101, a semiconductor storing device in which pieces of data corresponding to a bit width of a memory cell array are read out from or written in a plurality of memory cells of the memory cell array in one access operation even though the top memory cell placed at the top among the memory cells is placed in the middle of a row of memory cells.
The object is achieved by the provision of a semiconductor storing device including a memory cell array having a plurality of memory cells, a plurality of memory cell blocks, a plurality of word lines, a plurality of bit lines, a first row address decoder, a second row address decoder and a word line control unit.
The memory cells are disposed in a matrix of a plurality of columns respectively extending in a column direction and a plurality of rows respectively extending in a row direction from a first column position to a second column position, and a plurality of addresses are assigned to the memory cells in one-to-one correspondence. The memory cell blocks are disposed in parallel to each other in the row direction, and each memory cell block has the memory cells of a group of columns to have a prescribed bit width in the row direction. Each word line is connected with the memory cells of the memory cell array placed in one row. Each bit line is connected with the memory cells of the memory cell array placed in one column. The first row address decoder selects one word line from the word lines according to a first row address signal. The second row address decoder selects one word line corresponding to a specific address group, which is higher than an address group of the word line selected by the first row address decoder and is nearest to the address group of the word line among address groups of the word lines, from the word lines according to a second row address signal. Finally, the word line control unit controls the word line selected by the first row address decoder to be set to an active state in one memory cell block or memory cell blocks placed on the side of the second column position and controlling the word line selected by the second row address decoder, in the remaining memory cell block or the remaining memory cell blocks or no remaining memory cell block placed on the side of the first column position, to be set to an active state.
In the above configuration, the word line of the specific address group, which is higher than that of the word line selected by the first row address decoder and is nearest to that of the word line among address groups of the word lines, is selected in the second row address decoder. Thereafter, by the word line control unit, the word line selected by the first row address decoder is set to an active state in one memory cell block or memory cell blocks placed on the side of the second column position, and the word line selected by the second row address decoder is set to an active state in the remaining memory cell block or the remaining memory cell blocks or no remaining memory cell block placed on the side of the first column position. Thereafter, pieces of one-bit data are read out from or written in specific memory cells of the word lines set to the active state in one access operation. In this case, the top specific memory cell of the word line selected by the first row address decoder and set to the active state is not necessarily placed on the top position (or the first column position) of the corresponding row. Also, because the pieces of one-bit data are read out from or written in the specific memory cells of all the memory cell blocks, pieces of one-bit data corresponding to a bit width of the memory cell array (or the bit widths of all the memory cell blocks) are read out from or written in the specific memory cells.
Accordingly, even though a top memory cell placed at the top among a plurality of memory cells of pieces of one-bit data planed to be read out or written is placed in the middle of a row of memory cells, the pieces of one-bit data corresponding to a bit width of the memory cell array can be read out from or written in the memory cells of the memory cell array in one access operation.
The object is also achieved by the provision of a semiconductor storing device including the memory cell array having the memory cells, a plurality of memory cell blocks, a plurality of word lines, a row address decoder, a plurality of bit lines, a plurality of bit select lines, a first column address decoder, a second column address decoder, a plurality of bit selectors and a bit line control unit.
The memory cell blocks are disposed in parallel to each other in the row direction, and each memory cell block has the N memory cells (N denotes an integral number equal to or higher than two) for each row. Each word line is connected with the memory cells of the memory cell array placed in one row. The row address decoder selects one of the word lines according to a row address signal. Each bit line is connected with the memory cells of the memory cell array placed in one column. The bit select lines are related to the bit lines of each memory cell block in one-to-one correspondence, and the number bit select lines is equal to N. The first column address decoder selects one bit select line from the bit select lines according to a first column address signal. The second column address decoder selects one bit select line corresponding to one bit line of a specific address group, which is higher than an address group of the bit line corresponding to the bit select line selected by the first column address decoder and is nearest to the address group of the bit line among address groups of the bit lines of one memory cell block, according to a second column address signal. The bit selectors is disposed in correspondence to the memory cell blocks respectively and connected with the bit select lines, and each bit selector selects the bit line corresponding to the bit select line selected by the first column address decoder or the bit line corresponding to the bit select line selected by the second column address decoder from the bit lines of the corresponding memory cell block. Finally, the bit line control unit controls one bit selector or each of bit selectors corresponding to one memory cell block or each of memory cell blocks placed on the side of the second column position to select the bit line corresponding to the bit select line selected by the first column address decoder and controls one bit selector or each of bit selectors or no bit selector corresponding to the remaining memory cell block or each of the remaining memory cell blocks or no remaining memory cell block placed on the side of the first column position to select the bit line corresponding to the bit select line selected by the second column address decoder.
In the above configuration, the bit select line corresponding to the bit line of the specific address group, which is higher than that of the bit line corresponding to the bit select line selected by the first column address decoder and is nearest to that of the bit line among those of the bit lines of the memory cell block, is selected by the second column address decoder. Thereafter, under the control of the bit line control unit, the bit line corresponding to the bit select line selected in the first column address decoder is selected in one memory cell block or each of memory cell blocks placed on the side of the second column position, and the bit line corresponding to the bit select line selected by the second column address decoder is selected in the remaining memory cell block or each of the remaining memory cell blocks or no remaining memory cell block placed on the side of the first column position.
Accordingly, even though a top memory cell placed at the top among a plurality of memory cells of pieces of one-bit data planed to be read out or written is placed in the middle of a row of memory cells, the pieces of one-bit data corresponding to a bit width of the memory cell array can be read out from or written in the memory cells of the memory cell array in one access operation.
The object is also achieved by the provision of a semiconductor storing device including a row address decoder and a word line changing unit.
The row address decoder selects one word line from the word lines according to a row address signal. The word line changing unit sets the word line selected by the row address decoder to an active state in one memory cell block or memory cell blocks placed on the side of the second column position and changes the word line selected by the row address decoder, in the remaining memory cell block or the remaining memory cell blocks or no remaining memory cell block placed on the side of the first column position, to another word line corresponding to a specific address group, which is higher than an address group of the word line selected by the row address decoder and is nearest to the address group of the word line among address groups of the word lines, to set the changed word line to an active state.
In the above configuration, in the word line changing unit, the word line selected by the row address decoder is set to an active state in one memory cell block or memory cell blocks placed on the side of the second column position. Also, in the remaining memory cell block or the remaining memory cell blocks or no remaining memory cell block placed on the side of the first column position, the word line selected by the row address decoder is changed to another word line corresponding to a specific address group, which is higher than that of the word line selected by the row address decoder and is nearest to that of the word line among address groups of the word lines, to set the changed word line to an active state.
Accordingly, even though a top memory cell placed at the top among a plurality of memory cells of pieces of one-bit data planed to be read out or written is placed in the middle of a row of memory cells, the pieces of one-bit data corresponding to a bit width of the memory cell array can be read out from or written in the memory cells of the memory cell array in one access operation.
The object is also achieved by the provision of a semiconductor storing device including the bit line control unit and a word line changing unit.
The word line changing unit sets the word line selected by the row address decoder to an active state in the memory cell block or the memory cell blocks in which the bit line corresponding to the bit select line selected by the column address decoder is set to the active state by the bit line control unit, changes the word line selected by the row address decoder, in the remaining memory cell block or the remaining memory cell blocks or no remaining memory cell block in which the bit line of the specific address group is set to the active state by the bit line control unit, to another word line corresponding to a specific address group, which is higher than an address group of the word line selected by the row address decoder and is nearest to the address group of the word line among address groups of the word lines, in a case where the word line selected by the row address decoder does not correspond to the highest address group among the address groups of the word lines, changes the word line selected by the row address decoder, in the remaining memory cell block or the remaining memory cell blocks or no remaining memory cell block in which the bit line of the specific address group is set to the active state by the bit line control unit, to the word line corresponding to the lowest address group among the address groups of the word lines, in a case where the word line selected by the row address decoder corresponds to the highest address group among the address. groups of the word lines, and sets each of the changed word lines to an active state.
In the above configuration, in cases where the word line selected by the row address decoder is connected with the memory cells of an address group which is highest among address groups of the word lines, the word line corresponding to the highest address group is set to an active state in one memory cell block or memory cell blocks placed on the side of the second column position by the word line changing unit, and the word line corresponding to the lowest address group among those of the word lines is set to an active state by the word line changing unit in the remaining memory cell block or the remaining memory cell blocks or no remaining memory cell block placed on the side of the first column position. Also, in the bit line control unit, the bit line corresponding to the bit select line selected by the column address decoder is set to an active state in the memory cell block(s) in which the word line corresponding to the highest address group is set to the active state, and the bit line of the specific address group, which is higher than that of the bit line corresponding to the bit select line selected by the column address decoder and is nearest to the address group of the bit line among address groups of the bit lines of one memory cell block, is set to an active state in the remaining memory cell block(s) in which the word line corresponding to the lowest address group is set to the active state.
Accordingly, even though a top memory cell placed at the top among a plurality of memory cells of pieces of one-bit data planed to be read out or written is placed in the middle of a row of memory cells, the pieces of one-bit data corresponding to a bit width of the memory cell array can be read out from or written in the memory cells of the memory cell array in one access operation.
The object is also achieved by the provision of a semiconductor storing device including the word line changing unit and a bit line control unit
The bit line control unit controls one bit selector or each of bit selectors corresponding to the memory cell block or each of the memory cell blocks, in which the word line selected by the row address decoder is set to the active state by the word line changing unit, to select the bit line corresponding to the bit select line selected by the column address decoder, controls one bit selector or each of bit selectors or no bit selector corresponding to the remaining memory cell block or each of the remaining memory cell blocks or no remaining memory cell block, in which the word line corresponding to the specific address group is set to the active state by the word line changing unit, to select one bit line of a specific address group, which is higher than an address group of the bit line corresponding to the bit select line selected by the column address decoder and is nearest to the address group of the bit line among address groups of the bit lines of the corresponding memory cell block, from the bit lines of the corresponding memory cell block, in a case where the bit select line selected by the column address decoder does not correspond to the bit line of the highest address group, and to select the bit line of the lowest address group from among the bit lines of the remaining memory cell block in a case where the bit select line selected by the column address decoder corresponds to the bit line of the highest address group, and sets each of the selected bit lines of the memory cell blocks to an active state.
In the above configuration, in cases where the bit select line selected by the column address decoder corresponds to the bit line of the highest address group among those of the bit lines in one memory cell block, the bit line of the highest address group is set to an active state in the bit line control unit in one memory cell block or each of memory cell blocks placed on the side of the second column position, and the bit line of the lowest address group among those of the bit lines in one memory cell block is set to an active state in the bit line control unit in the remaining memory cell block or each of the remaining memory cell blocks or no remaining memory cell block placed on the side of the first column position. Also, in the word line changing unit, the word line selected by the row address decoder is set to an active state in the memory cell block(s) in which the bit line of the highest address group is set to the active state, and the word line of the specific address group, which is higher than that of the bit line corresponding to the bit select line selected by the column address decoder and is nearest to that of the bit line among address groups of the bit lines of one memory cell block, is set to the active state in the remaining memory cell block(s) in which the bit line of the lowest address group is set to the active state.
Accordingly, even though a top memory cell placed at the top among a plurality of memory cells of pieces of one-bit data planed to be read out or written is placed in the middle of a row of memory cells, the pieces of one-bit data corresponding to a bit width of the memory cell array can be read out from or written in the memory cells of the memory cell array in one access operation.